Semiconductor memory devices, e.g., dynamic random access memories (DRAMs), require high speed as well as high integration. A logic part such as a central processing unit (CPU) of semiconductor products becomes fast in its speed to process more data for a short time. Accordingly, an increase in speed as well as in a storage capacity of the semiconductor memory devices such as DRAMs becomes important.
A speed increase of the semiconductor memory devices can be generally realized using a metal wiring having low resistance. For example, a copper wiring is used to lower wiring resistance instead of a conventional aluminum wiring. An effort to reduce a delay due to a coupling noise also has been made. The coupling noise generally occurs due to the parasitic capacitance of a parasitic capacitor. Thus, the parasitic capacitance should be decreased to reduce the RC delay. To reduce the parasitic capacitance, an insulation film of low dielectric constant can be formed on a wiring portion, or decoupling capacitors for canceling out the parasitic capacitance can be formed around a cell region.
The decoupling capacitors have been formed using a gate-oxide film. However, as integration of the semiconductor devices increases, a capacity of the decoupling capacitors should be increased. Thus, it has been difficult to realize a high capacitance using a plate-type dielectric film such as the gate-oxide film.
A decoupling capacitor having a high capacity using a structure such as a cell capacitor has been studied. However, the structure of the cell capacitor was not easy to manufacture. A decoupling capacitor using a cell capacitor becomes available with a development of a square-type storage node of a capacitor-over-bit-line (COB) type, in which a capacitor is formed on a bit line. A decoupling capacitor of semiconductor memory devices according to a conventional art will be described below with reference to accompanying drawings.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor memory device. Referring to FIG. 1, the semiconductor memory devices 100 can be divided into a cell region A, where a cell capacitor is formed, and a decoupling capacitor region B. The cell capacitor includes storage nodes 135a, and a decoupling capacitor includes storage nodes 135b. These two different storage nodes 135a and 135b are formed on the respective buffer layers 131a and 131b. The buffer layers 131a and 131b connect the storage nodes 135a and 135b with the respective buried contacts 130a and 130b. 
Thus, as illustrated in FIG. 1, although disalignment is generated between the buried contacts 130a and 130b and the storage nodes 135a and 135b, the buffer layers 131a and 131b can properly connect the buried contacts 130a and 130b with the storage nodes 135a and 135b, respectively. The storage nodes 135a and 135b are formed within mold oxide films 132a and 132b, and the buried contacts 130a are formed within an inter-layer insulation film 127.
The buried contacts 130a of the cell region A is connected with a semiconductor substrate 105, more specifically, with a source/drain portion (not shown) confined by a device isolating region 110 through cell pads 125. The cell pads 125 are formed in a self-alignment structure created by word-line gates 120a and their lateral spacers 122. The word-line gates 120a include insulation films 115a, gate electrode films 117a, and capping films 119a. 
The buried contacts 130b of the decoupling capacitor region B are formed on a capping film 119b. A gate insulation film 115b, a gate electrode film 117b, and the capping film 119b are sequentially formed on the semiconductor substrate 105.
FIG. 2 is a plan view illustrating a decoupling capacitor of the semiconductor memory device according to the conventional technology of FIG. 1. As illustrated in FIG. 2, a decoupling capacitor 100B includes a plurality of storage nodes 135b formed on a buffer layer 131b. A plurality of plate electrodes 150b are formed on the storage nodes 135b. 
As integration of the memory device increases, a structure without the buffer layer 131a of the cell region A becomes available. Thus, in the decoupling capacitor region (region B of FIG. 1), a structure connecting the decoupling capacitor 100B with the buried contact 130b without the buffer layer 131b is in study.